Title :
A new and improved borderless contact (BLC) structure for high-performance Ti-salicide in sub-quarter micron CMOS devices
Author :
Liu, Wen-Chau ; Thei, Kong-Beng ; Wang, Wei-Chou ; Pan, Hsi-jen ; Wuu, Shou-Gwo ; Lei, Ming-Ta ; Wang, Chung-Shu ; Cheng, Shiou-Ying
Author_Institution :
Dept. of Electr. Eng., Nat. Cheng Kung Univ., Tainan, Taiwan
fDate :
7/1/2000 12:00:00 AM
Abstract :
We demonstrate a new and improved borderless contact (BLC) Ti-salicide process for the fabrication of sub-quarter micron CMOS devices. A low-temperature chemical vapor deposition (CVD) SiO/sub x/N/sub y/ film to act as the selective etching stop layer and the additional n/sup +/ and p/sup +/ source-drain double implant structure (DIS) are employed in the studied device. The additional n/sup +/ and p/sup +/ DIS can reduce the junction leakage current, which is usually enhanced by BLC etching near the edge of shallow trench isolation (STI). The process window is enlarged. Furthermore, the employed low-thermal oxynitride and high deposition rate can improve the salicide thermal stability and avoid the salicide agglomeration.
Keywords :
CMOS integrated circuits; ULSI; VLSI; etching; integrated circuit metallisation; thermal stability; titanium compounds; 0.24 to 0.25 micron; BLC Ti-salicide process; SiON; TiSi/sub 2/; borderless contact structure; chemical vapor deposited SiO/sub x/N/sub y/ film; high deposition rate; high-performance Ti-salicide; junction leakage current; low-temperature CVD SiO/sub x/N/sub y/ film; low-thermal oxynitride; salicide thermal stability; selective etching stop layer; shallow trench isolation; source-drain double implant structure; subquarter micron CMOS devices; CMOS process; CMOS technology; Chemical vapor deposition; Etching; Fabrication; Implants; Leakage current; MOS devices; Semiconductor films; Thermal stability;
Journal_Title :
Electron Device Letters, IEEE
