A novel simplified process for fabricating a very high density p-channel trench gate power MOSFET

Author

Kee Soo Nam ; Ju Wook Lee ; Sang-Gi Kim ; Tae Moon Roh ; Hoon Soo Park ; Jin Gun Koo ; Kyung Ik Cho

Author_Institution

Microelectron. Technol. Lab., Electron. & Telecommun. Res. Inst., Taejon, South Korea

Volume

21

Issue

7

fYear

2000

fDate

7/1/2000 12:00:00 AM

Firstpage

365

Lastpage

367

Abstract

A novel simplified fabrication method of a very high density p-channel trench gate power MOSFET using four mask layers and nitride/TEOS sidewall spacers is realized. The proposed process showed improved on-resistance characteristics of the device with increasing cell density and the cost-effective production capability due to the lesser number of processing steps. By using this process technique, a remarkably increased high density (100 Mcell/inch²) trench gate power MOSFET with a cell pitch of 2.5 μm could be effectively realized. The fabricated device had a low specific on-resistance of 1.1 m/spl Omega/-cm² with a breakdown voltage of -36 V.

Keywords

power MOSFET; semiconductor device breakdown; semiconductor technology; -36 V; 2.5 micron; PMOSFET; breakdown voltage; cost-effective production capability; four mask layer process; nitride/TEOS sidewall spacers; on-resistance characteristics; p-MOSFET; p-channel MOSFET; simplified fabrication process; trench gate power MOSFET; very high cell density; Battery management systems; Conductivity; Etching; Fabrication; MOSFET circuits; Materials science and technology; Moon; Power MOSFET; Production; Silicon;

fLanguage

English

Journal_Title

Electron Device Letters, IEEE

Publisher

ieee

ISSN

0741-3106

Type

jour

DOI

10.1109/55.847382

Filename

847382