DocumentCode :
1348793
Title :
Escape Routing in Modern Area Array Packaging: An Analysis of Need, Trend, and Capability
Author :
Jaiswal, Bhanu ; Roy, Mihir K. ; Titus, Albert H.
Author_Institution :
Intel Corp., Chandler, AZ, USA
Volume :
33
Issue :
1
fYear :
2010
Firstpage :
13
Lastpage :
18
Abstract :
With the increasing complexity in the die and package designs and ever increasing cost pressure in today´s microelectronic industry, the design for input/output (I/O) routing has assumed a vital role in the overall product design. This scenario is primarily driven by the increase in the I/O terminal counts in both die and package. Several authors have already described the possibility of using various escape routing models in order to maximize the number of I/Os in a given area. However, these models suffer from many drawbacks and fail to address the importance of processing factors and the actual manufacturing conditions. Therefore, a new design guideline for escape routing has been developed to achieve the maximum I/O density under the actual manufacturing, processing and cost related constraints. The correlation between the real world constraints and their impact on I/O routing has been explored and used as a foundation for developing design guidelines. This approach has been presented through a comprehensive case study that covers various design scenarios, provides the right set of real world trade-offs that need to be considered and simultaneously highlights the drawbacks in existing models.
Keywords :
network routing; packaging; product design; area array packaging; die-package designs; input-output routing; maximum I-O density; product design; Area array package; die-size; escape routing design; input/output (I/O) terminals; layer-count; micro-via; package substrate; trace width and spacing; two-layer routing;
fLanguage :
English
Journal_Title :
Advanced Packaging, IEEE Transactions on
Publisher :
ieee
ISSN :
1521-3323
Type :
jour
DOI :
10.1109/TADVP.2009.2035304
Filename :
5345717
Link To Document :
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