On the design of selective coefficient DCT module

Author

Lu, Chung-Yen ; Wen, Kuei-Ann

Author_Institution

Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan

Volume

8

Issue

2

fYear

1998

fDate

4/1/1998 12:00:00 AM

Firstpage

143

Lastpage

146

Abstract

An innovative selective coefficient discrete cosine transform (SCDCT) architecture is proposed which is designed for selective coefficient computation and straightforward row-column computation. Having these features, the selective coefficient DCT core will fit for various area/speed requirements. It can save the transposition delay to simplify the computation flow of two-dimensional (2-D) DCT and, in view of circuit implementation, SCDCT is multiply-free and thus area/speed efficient

Keywords

digital circuits; discrete cosine transforms; modules; network synthesis; transform coding; video coding; 2-D DCT; SCDCT; area requirements; circuit implementation; computation flow; design; row-column computation; selective coefficient DCT module; selective coefficient computation; selective coefficient discrete cosine transform architecture; speed requirements; transposition delay; two-dimensional DCT; video coding; Bandwidth; Circuits; Computer architecture; Delay; Discrete cosine transforms; Helium; Image coding; Matrix decomposition; Two dimensional displays; Video compression;

fLanguage

English

Journal_Title

Circuits and Systems for Video Technology, IEEE Transactions on

Publisher

ieee

ISSN

1051-8215

Type

jour

DOI

10.1109/76.664099

Filename

664099