Title :
Scalable Methods for Analyzing the Circuit Failure Probability Due to Gate Oxide Breakdown
Author :
Fang, Jianxin ; Sapatnekar, Sachin S.
Author_Institution :
Dept. of Electr. & Comput. Eng., Univ. of Minnesota, Minneapolis, MN, USA
Abstract :
Gate oxide breakdown is an important reliability issue that has been widely studied at the individual transistor level, but has seen very little work at the circuit level. We first develop an analytic closed-form model for the failure probability (FP) of a large digital circuit due to this phenomenon. The new approach accounts for the fact that not every breakdown leads to circuit failure, and shows a 4.8-6.2× relaxation of the predicted lifetime with respect to the pessimistic area-scaling method for nominal process parameters. Next, we extend the failure analysis to include the effect of process variations, and derive that the circuit FP at a specified time instant has a lognormal distribution due to process variations. Circuits with variations show 19%-24% lifetime degradation against nominal analysis and 4.7-5.9× lifetime relaxation against area-scaling method under variations. Both parts of our work are verified by extensive simulations and proved to be effective, accurate and scalable.
Keywords :
CMOS digital integrated circuits; MOSFET; failure analysis; integrated circuit reliability; log normal distribution; probability; CMOS digital circuit; FP; circuit failure probability analysis; gate oxide breakdown; lifetime degradation; lognormal distribution; nominal analysis; nominal process parameter; pessimistic area-scaling method; reliability issue; scalable method; transistor level; Electric breakdown; Failure analysis; Integrated circuit modeling; Integrated circuit reliability; Logic gates; Stress; Transistors; Circuit reliability; failure analysis; oxide breakdown; process variation;
Journal_Title :
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
DOI :
10.1109/TVLSI.2011.2166568
