Multilevel logic synthesis

Author

Brayton, R.K. ; Hachtel, G.D. ; Sangiovanni-Vincentelli, A.L.

Author_Institution

Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA

Volume

78

Issue

2

fYear

1990

fDate

2/1/1990 12:00:00 AM

Firstpage

264

Lastpage

300

Abstract

A survey of logic synthesis techniques for multilevel combinational logic is presented. The goal is to provide more in-depth background and perspective for people interested in pursuing or assessing some of the topics in this emerging field. Introductions, capsule summaries, and, in some cases, detailed analysis of the synthesis methods that have become established as practically significant are provided. Also included are some methods that have theoretical interest and potential for future impact. The discussion covers notation and definitions, representation of the network and nodes, logic decomposition/restructuring, logic optimization/minimization, logic synthesis and testing, and technology mapping

Keywords

circuit layout CAD; integrated logic circuits; logic CAD; capsule summaries; definitions; detailed analysis; in-depth background; logic decomposition; logic minimisation; logic synthesis; logic synthesis techniques; multilevel combinational logic; multilevel logic synthesis; notation; perspective; survey; synthesis methods; technology mapping; testing; Application specific integrated circuits; Design automation; Integrated circuit synthesis; Logic design; Logic devices; Logic testing; Network synthesis; Programmable logic arrays; Signal synthesis; Silicon;

fLanguage

English

Journal_Title

Proceedings of the IEEE

Publisher

ieee

ISSN

0018-9219

Type

jour

DOI

10.1109/5.52213

Filename

52213