Title :
One-dimensional discrete-time CNN with multiplexed template-hardware
Author :
Manganaro, Gabriele ; De Gyvez, Jose Pineda
fDate :
5/1/2000 12:00:00 AM
Abstract :
This paper presents a novel discrete-time and fully programmable cellular neural network (CNN) suitable for processing one-dimensional (1-D) signals. As 1-D signals are typically very long sequences, the system consists of a linear analog shift register for data I/O coupled to a 1×n CNN array. In addition to the 1-D CNN architecture, a unique feature of our implementation is that the number of multipliers needed to implement both CNN templates has been minimized. This is conceivable because the multipliers are multiplexed between the A*y and B*u products during alternating phases of the controlling clock. The CNN system has been implemented in current mode based on the S2I technique using MOSIS Orbit 2 μm CMOS technology. The paper presents a thorough behavioral analysis of the new architecture, circuit-level implementations, and corresponding measured experimental results
Keywords :
CMOS analogue integrated circuits; VLSI; analogue processing circuits; cellular neural nets; current-mode circuits; discrete time systems; neural chips; neural net architecture; programmable circuits; shift registers; video signal processing; 1D discrete-time CNN; 1D signal processing; 2 micron; CMOS VLSI chip; MOSIS Orbit CMOS technology; S2I technique; behavioral analysis; circuit-level implementations; current mode; linear analog shift registers; multiplexed template-hardware; one-dimensional signals; programmable cellular neural network; video signals; CMOS technology; Cellular neural networks; Clocks; Error correction; Frequency; Gain; Hardware; Shift registers; Signal processing; Solid state circuits;
Journal_Title :
Circuits and Systems I: Fundamental Theory and Applications, IEEE Transactions on