Gigahertz-Range Analysis of Impedance Profile and Cavity Resonances in Multilayered PCBs

As is known, undesired simultaneous switching noise produced by high-speed digital integrated circuits (ICs) and power vias may propagate along parallel-plane structures of multilayer printed circuit boards (PCBs) and IC packages, which act as parallel-plane cavity resonators. To minimize effects of the parallel-plane cavities, we need to minimize the impedance profile of a PCB power bus in the frequency range of interest. We can minimize the impedance profile by reducing power bus plane spacings, and by using local and global decoupling techniques that employ decoupling capacitors. But, in the gigahertz-range, discrete capacitors are not efficient due to the parasitic inductance of their connections to the power bus. In this paper, in addition to the analysis of cavity-mode resonances in multilayered PCBs, we derived expressions for the impedance envelope that can be used for predicting the impedance profile of a power bus. This theoretical approach and the derived envelope expressions are confirmed analytically by the cavity-model method, by a full-wave field solver, and by laboratory measurements carried out by a network analyzer.