Post global routing crosstalk synthesis

For the generation of a risk-free layout solution of a chip, crosstalk synthesis should be pursued at various stages in the routing process. This paper proposes a post global routing crosstalk optimization approach, which to our knowledge, is the first to estimate and reduce crosstalk risk at the global routing level. It consists of two parts: region-based crosstalk risk estimation and crosstalk risk reduction at the global routing level. In the first part, crosstalk risk graphs are first introduced for each routing region representing its current crosstalk situation. The crosstalk risk of each region, which indicates whether a risk-free routing solution of the region is possible, is then quantitatively defined and estimated using a graph-based approach. In the second part, the risk tolerance bound of each net is partitioned appropriately among its routing regions via integer linear programming for accurate (minimized) crosstalk risk estimation. If high risk regions still exist after bound partitioning, net ripping-up and rerouting is applied to reduce their crosstalk risks. At the end of the entire optimization process, a risk-free global routing solution is obtained together with partitions of nets´ risk tolerance bounds which reflect the current crosstalk situation of the chip. These can greatly facilitate the generation of a risk-free final solution at later stages in the layout process. The proposed approach has been implemented and tested on CBL/NCSU benchmarks and the experimental results are very promising