DocumentCode :
1349657
Title :
Nonscan design-for-testability techniques using RT-level design information
Author :
Dey, Sujit ; Potkonjak, Miodrag
Author_Institution :
C&C Res. Labs., NEC Res. Inst., Princeton, NJ, USA
Volume :
16
Issue :
12
fYear :
1997
fDate :
12/1/1997 12:00:00 AM
Firstpage :
1488
Lastpage :
1506
Abstract :
This paper presents nonscan design-for-testability (DFT) techniques applicable to register-transfer (RT)-level data path circuits. Knowledge of high-level design information, in the form of the RT-level structure, as well as the functions of the RT-level components is utilized to develop effective nonscan DFT techniques. Instead of conventional techniques of selecting flip-flops (FF´s) to make systems controllable/observable, execution units (EXU´s) are selected using the EXU S-graph introduced in this paper. Controllability/observability points can be implemented using register files and constants. We introduce the notion of k-level controllable and observable loops and demonstrate that it suffices to make all the loops k-level controllable/observable, k>0, to achieve very high test efficiency. The new testability measure eliminates the need by traditional DFT techniques to make all loops directly (zero-level) controllable/observable, reducing significantly the hardware overhead required and making the nonscan DFT approach feasible and effective. We discuss ways of avoiding the formation of reconvergent regions while adding test points to make loops k-level controllable/observable. We introduce dual points, which utilize the different controllability/observability levels of loops, to make one loop controllable while making another loop observable. We present efficient algorithms to add the minimal hardware possible to make all loops in the data path k-level controllable/observable, without the use of scan FF´s. The nonscan DFT techniques were applied to several data path circuits. The experimental results demonstrate the effectiveness of the k-level testability measure, and the use of distributed and dual points, to generate easily testable data paths with reduced hardware overhead. The hardware overhead and the test application time required for the nonscan designs are significantly lower than for the partial scan designs. Most significantly, the experimental results demonstrate the ability of the RT-level DFT techniques to produce nonscan testable data paths, which can be tested at-speed
Keywords :
controllability; design for testability; flip-flops; graph theory; high level synthesis; logic testing; observability; sequential circuits; RT-level design information; S-graph; execution units; hardware overhead; high-level design information; k-level controllable loops; k-level observable loops; nonscan design-for-testability techniques; reconvergent regions; register-transfer (RT)-level data path circuits; test application time; test efficiency; Circuit testing; Controllability; Design for testability; Flip-flops; Hardware; Laboratories; Logic testing; National electric code; Observability; Sequential analysis;
fLanguage :
English
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
0278-0070
Type :
jour
DOI :
10.1109/43.664230
Filename :
664230
Link To Document :
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