Design Framework for Soft-Error-Resilient Sequential Cells

Author

Lee, Hsiao-Heng Kelin ; Lilja, Klas ; Bounasser, Mounaim ; Linscott, Ivan ; Inan, Umran

Author_Institution

VLF Group in the Dept. of Electr. Eng., Stanford Univ., Stanford, CA, USA

Volume

58

Issue

6

fYear

2011

Firstpage

3026

Lastpage

3032

Abstract

This paper presents a design framework for soft-error-resilient sequential cells, by introducing a new sequential cell called LEAP-DICE and evaluating it against existing circuit techniques in the “soft error resilience-power-delay-area” design space in an 180 nm CMOS test chip. LEAP-DICE, which employs both circuit and layout techniques, achieved the best soft error performance with a 2,000X improvement over the reference D flip-flop with moderate design costs. This study also discovered new soft error effects related to operating conditions.

Keywords

CMOS integrated circuits; circuit layout; flip-flops; integrated circuit design; radiation hardening (electronics); sequential circuits; CMOS test chip; LEAP-DICE; circuit technique; design framework; flip-flop; layout technique; radiation hardening; size 180 nm; soft error performance; soft error resilience-power-delay-area; soft-error-resilient sequential cells; CMOS integrated circuits; Latches; Layout; Radiation hardening; Resilience; Sequential circuits; Transistors; CMOS integrated circuits; DICE; LEAP; radiation hardening; sequential circuits; soft error;

fLanguage

English

Journal_Title

Nuclear Science, IEEE Transactions on

Publisher

ieee

ISSN

0018-9499

Type

jour

DOI

10.1109/TNS.2011.2168611

Filename

6044739