Abstract :
The Texas Instruments VelociTI architecture is a very long instruction word (VLIW) architecture. The TMS320C6x family of digital signal processors (DSPs) is the first to employ the VelociTI architecture, with the TMS3206201 (C6201) being the first device in this family. The C6201 is based on the fixed-point TMS320C62x (C62x) CPU. This article describes the VelociTI VLIW architecture and discusses the C62x, C67x, C6201, and the VelociTI development tools. An overview of the VelociTI including architectural principles, data path, instruction set, and pipeline operation is presented, and both the C62x fixed-point CPU and the C67x floating-point CPU are described. A summary of the C62x benchmark performance is also presented. The chip-level support outside the CPU that allows the C6201 to operate in a variety of high-performance DSP environments is also described. An overview of the C6x development environment is also given, demonstrating the breadth of the development environment and illustrating the programming methodology. The article concludes with a performance analysis of the C compiler
Keywords :
digital signal processing chips; floating point arithmetic; instruction sets; parallel architectures; pipeline processing; program compilers; reduced instruction set computing; C compiler; C62x; C67x; TMS3206201; Texas Instruments; VLIW DSP architecture; VelociTI architecture; VelociTI development tools; VelociTI processing; benchmark performance; chip-level support; data path; development environment; digital signal processors; fixed-point CPU; fixed-point TMS320C62x; floating-point CPU; instruction set; pipeline operation; programming methodology; very long instruction word; Arithmetic; Computer aided instruction; Delay; Digital signal processing; Digital signal processing chips; Digital signal processors; Frequency; Functional programming; Instruments; Performance analysis; Pipeline processing; Pipelines; Reduced instruction set computing; Registers; Signal processing algorithms; VLIW;
