High-speed demonstration of a superconducting pseudo-random bit-sequence generator

Author

Wang, Z. ; Jeffery, M.J. ; Perold, W.J. ; Van Duzer, T.

Author_Institution

Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA

Volume

10

Issue

2

fYear

2000

fDate

6/1/2000 12:00:00 AM

Firstpage

1593

Lastpage

1597

Abstract

This paper describes the design, analysis and test results for a 4-bit pseudo-random bit-sequence generator (PRBSG) implemented with complementary output switching logic (COSL) gates. The PRBSG was optimized using a Monte Carlo simulation method for 10-GHz operation. The circuit has been fabricated using niobium technology with critical current density of 1 kA/cm/sup 2/ and sheet resistance of 1 /spl Omega//sq. The 4-bit PRBSG consists of 12 gates and its area is 1530/spl times/950 /spl mu/m/sup 2/. It has been fully tested with a three-phase power supply, and its power consumption is 0.15 mW. The correct operations have been verified experimentally at clock frequencies of up to 2 GHz.

Keywords

Monte Carlo methods; binary sequences; random number generation; superconducting logic circuits; 0.15 W; 2 to 10 GHz; 4 bit; Monte Carlo simulation; Nb; complementary output switching logic gate; critical current density; high-speed circuit; niobium technology; sheet resistance; superconducting pseudo-random bit-sequence generator; Circuit testing; Critical current density; Energy consumption; Logic design; Logic gates; Logic testing; Niobium; Optimization methods; Power supplies; Superconducting logic circuits;

fLanguage

English

Journal_Title

Applied Superconductivity, IEEE Transactions on

Publisher

ieee

ISSN

1051-8223

Type

jour

DOI

10.1109/77.848306

Filename

848306