DocumentCode :
135106
Title :
On multi-cycle path support in model based high-level synthesis
Author :
Karfa, Chandan ; Jain, Sheetal
Author_Institution :
Synopsys (India) Pvt. Ltd., India
fYear :
2014
fDate :
Feb. 28 2014-March 2 2014
Firstpage :
253
Lastpage :
258
Abstract :
Multi-cycle paths (MCPs) are commonly used by designers as an efficient way to relax the timing constraints on eligible paths in their designs. MCP directs synthesis tools to relax the optimization on the specified paths. The MCP constraints are widely used in the Register Transfer Level (RTL) designs and are propagated to downstream tools. With the evolution of high level synthesis (HLS) tools, design entry and the constraints have to be specified at a higher level of abstraction. In addition, majority of the HLS users are system level designs or DSP experts who have little knowledge of RTL implementation flows. Hence, it is important for HLS tools to provide a methodology for specifying MCP constraints at a higher level of abstraction, consider the MCP paths during HLS and also forward annotate the MCP constraints to the RTL implementation tools. In this paper, we have created such a methodology for Synopsys Synphony model compiler (SMC), a model based HLS tool. To the best of our knowledge, MCP is supported for the first time in model based HLS flow. The effectiveness of specifying MCP on higher abstraction level is demonstrated on sample example designs.
Keywords :
logic design; network synthesis; sequential circuits; DSP; HLS tools; MCP constraint specification; MCP directs synthesis tools; RTL designs; RTL implementation flows; SMC; Synopsys Synphony model compiler; design entry; downstream tools; high level synthesis tools; model based high-level synthesis; multicycle path support; multicycle paths; register transfer level designs; sequential circuit; system level designs; timing constraints; Application specific integrated circuits; Clocks; Delays; Digital signal processing; Registers; Software packages; Digital Signal Processing; High-Level Synthesis; Multi-cycle path;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Students' Technology Symposium (TechSym), 2014 IEEE
Conference_Location :
Kharagpur
Print_ISBN :
978-1-4799-2607-7
Type :
conf
DOI :
10.1109/TechSym.2014.6808056
Filename :
6808056
Link To Document :
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