DocumentCode
1351134
Title
Solid state: 100 000+ gates on a chip: Mastering the minutia: The submicron geometries needed for VLSI have put IC makers on a new learning curve; object, to perfect feature delineation techniques
Author
Gossen, R.N.
Author_Institution
Texas Instruments Inc., Dallas, TX, USA
Volume
16
Issue
3
fYear
1979
fDate
3/1/1979 12:00:00 AM
Firstpage
42
Lastpage
42
Abstract
Established process technology and manufacturing techniques will no longer do; the 64 kbit RAM demands a quantum jump beyond them. It is a prelude to very large-scale integration (VLSI), or the placing of more than 100000 logic gates on a single chip. Primarily facing obsolescence is the present technique of photolithography as it affects feature delineation, because the wavelength of light used to expose IC mask patterns has become a significant percentage of the line width being printed. And after photolithography, conventional wet-chemical etching must also go; it also contributes to insufficient feature delineation. Meanwhile airborne particles that can become tiny topological defects in the finished water surface must now be virtually eliminated. All of these problems were encountered in the development of the 64-kbit RAM, and they were overcome by breaking new ground in processing techniques.
Keywords
field effect transistor circuits; integrated circuit technology; integrated memory circuits; large scale integration; random-access storage; 64 k RAM; VLSI; airborne particles; lithography; over 100000 gates/chip; processing techniques; Geometry; Logic gates; Production; Random access memory; Solids; Very large scale integration;
fLanguage
English
Journal_Title
Spectrum, IEEE
Publisher
ieee
ISSN
0018-9235
Type
jour
DOI
10.1109/MSPEC.1979.6367946
Filename
6367946
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