DocumentCode :
135125
Title :
500 MHz differential latched current comparator for calibration of current steering DAC
Author :
Sarkar, Santanu ; Banerjee, Swapna
Author_Institution :
Dept. of Electron. & Electr. Commun. Eng., Indian Inst. of Technol., Kharagpur, Kharagpur, India
fYear :
2014
fDate :
Feb. 28 2014-March 2 2014
Firstpage :
309
Lastpage :
312
Abstract :
This paper proposes the design techniques of high performance current comparator which can sense a minimum change of 8 nA for 10 μA input current. The current comparator shows fast response with 0.95 ns delay for an input current difference of 0.1 μA peak-to-peak and it can work up to 500 MHz clock frequency. The use of low impedance trans-impedance stage makes it faster and the preamplifier removes kickback noise. Using latch at the end of comparator provides a faster response. The dynamic comparator is pre-charged to VDD during low clock phase to remove the memory effects. The current comparator has been designed in 180 nm CMOS process with 1.8 V supply. The comparator shows an average power consumption of 697 μW for 10 μA input current.
Keywords :
CMOS integrated circuits; current comparators; flip-flops; operational amplifiers; preamplifiers; CMOS; current 0.1 muA; current 10 muA; current 8 nA; current steering DAC calibration; differential latched current comparator; frequency 500 MHz; kickback noise; low impedance trans-impedance stage; memory effects; power 697 muW; preamplifier; size 180 nm; time 0.95 ns; voltage 1.8 V; CMOS integrated circuits; Calibration; Clocks; Delays; Impedance; Latches; Noise; Calibration; Current Comparator; Current subtractor; Current-steering DAC; High performance com-parator; Low delay comparator; Matching;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Students' Technology Symposium (TechSym), 2014 IEEE
Conference_Location :
Kharagpur
Print_ISBN :
978-1-4799-2607-7
Type :
conf
DOI :
10.1109/TechSym.2014.6808066
Filename :
6808066
Link To Document :
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