Title :
Evolutionary graph generation system with symbolic verification for arithmetic circuit design
Author :
Homma, N. ; Aoki, T. ; Higuchi, T.
Author_Institution :
Dept. of Syst. Inf. Sci., Tohoku Univ., Sendai, Japan
fDate :
5/25/2000 12:00:00 AM
Abstract :
A novel graph-based evolutionary optimisation technique for arithmetic circuit synthesis is proposed. Symbolic verification of the generated circuit structures is introduced to accelerate the time-consuming evolution process. The evolutionary graph generation (EGG) system based on the proposed technique can successfully generate the optimal 16-bit constant-coefficient multiplier within ∼2.2 h.
Keywords :
digital arithmetic; 16 bit; arithmetic circuit design; arithmetic circuit synthesis; constant-coefficient multiplier; evolutionary graph generation system; evolutionary optimisation technique; symbolic verification;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:20000704
