• DocumentCode
    1352542
  • Title

    Low-area, pipelined conversion from signed-binary, to two´s-complement, number representation

  • Author

    Blair, G.M.

  • Author_Institution
    Dept. of Electr. Eng., Edinburgh Univ., UK
  • Volume
    32
  • Issue
    20
  • fYear
    1996
  • fDate
    9/26/1996 12:00:00 AM
  • Firstpage
    1866
  • Lastpage
    1867
  • Abstract
    A new architecture is proposed for the conversion of numbers from signed-binary to two´s-complement representation, where the former arrives in a skewed, most-significant-digits-first format, due to pipelined arithmetic operations
  • Keywords
    computer architecture; integrated logic circuits; pipeline arithmetic; low-area implementation; pipelined arithmetic operations; pipelined conversion; signed-binary number representation; skewed most-significant-digits-first format; two´s-complement number representation;
  • fLanguage
    English
  • Journal_Title
    Electronics Letters
  • Publisher
    iet
  • ISSN
    0013-5194
  • Type

    jour

  • DOI
    10.1049/el:19961257
  • Filename
    535161
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1352542