The use of RTL descriptions in accurate timing verification and test generation [VLSI]

The authors discuss the use of high-level information in two major problems of VLSI system design: (1) accurate timing verification to eliminate false paths due to reconvergent fan-out, redundancy, and control signal constraints, and (2) testing for stuck-at-faults. The register-transfer-level (RTL) descriptions provide the set of control signals for valid data operations. Using this set of control signals, the timing verifier can perform an efficient estimation of critical path delays for only valid data transfers. This approach to critical path justification can be extended to test generation for a class of sequential circuits where all latches and memory elements can be explicitly identified. Test generation for complex VLSI circuits composed of many interconnected modules is discussed. Sequential propagation and justification of signals are carried out using the data flow information. Results based on an implementation of the algorithms are presented