Design of submicrometer CMOS differential pass-transistor logic circuits

Author

Pasternak, John H. ; Salama, C. Andre T

Author_Institution

Dept. of Electr. Eng., Toronto Univ., Ont., Canada

Volume

26

Issue

9

fYear

1991

fDate

9/1/1991 12:00:00 AM

Firstpage

1249

Lastpage

1258

Abstract

The interaction between the architectural features of CMOS differential pass-transistor logic (DPTL) and the submicron process technology used to implement it are examined. Techniques that exploit the noise immunity associated with the DPTL architecture are presented to effectively enable signal-swing reductions that result in increased speed. The extent to which DPTL can benefit from this signal-swing/speed tradeoff is examined by investigating the impact of device scaling on DPTL operation. A novel DPTL buffer that enables the implementation of a single-phase clocking scheme and the exchange of signal swing for increased circuit speed is proposed. Experimental results are provided

Keywords

CMOS integrated circuits; buffer circuits; integrated logic circuits; logic design; scaling circuits; timing circuits; 0.8 micron; DPTL architecture; buffer; circuit speed; device scaling; differential pass-transistor logic; logic circuits; noise immunity; predischarging buffer; prescaler; signal-swing reductions; single-phase clocking scheme; submicrometer CMOS; submicron process technology; CMOS logic circuits; CMOS process; CMOS technology; Circuit noise; Clocks; Degradation; Logic circuits; Multiplexing; Noise reduction; Wafer scale integration;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.84941

Filename

84941