A Routing-Aware ILS Design Technique

Author

Banerjee, Shibaji ; Mathew, Jimson ; Pradhan, Dhiraj K. ; Bhattacharya, Bhargab B. ; Mohanty, Saraju P.

Author_Institution

Dept. of Comput. Sci., Univ. of Bristol, Bristol, UK

Volume

19

Issue

12

fYear

2011

Firstpage

2335

Lastpage

2338

Abstract

The Illinois Scan Architecture (ILS) consists of several scan path segments and is useful in reducing test application time and test data volume for high density chips. In this paper, we propose a scheme of layout-aware as well as coverage-driven ILS design. The partitioning of the flip-flops into ILS segments is determined by their geometric locations, whereas the set of the flip-flops to be placed in parallel is determined by the minimum incompatibility relations among the corresponding bits of a test set, to enhance fault coverage in broadcast mode. As a result, the number of serial test patterns also reduces.

Keywords

design for testability; flip-flops; logic testing; network routing; Illinois scan architecture; broadcast mode; fault coverage; flip-flops; geometric locations; routing-aware ILS design technique; scan path segments; serial test patterns; Algorithm design and analysis; Circuit faults; Flip-flops; Partitioning algorithms; Power dissipation; Wiring; DFT; Illinois Scan Architecture (ILS); scan testing;

fLanguage

English

Journal_Title

Very Large Scale Integration (VLSI) Systems, IEEE Transactions on

Publisher

ieee

ISSN

1063-8210

Type

jour

DOI

10.1109/TVLSI.2010.2078526

Filename

5604348