A programmable CORDIC chip for digital signal processing applications

Author

Timmermann, D. ; Hahn, H. ; Hosticka, B.J. ; Schmidt, G.

Author_Institution

Fraunhofer Inst. of Microelectron. Circuits & Syst., Duisburg, Germany

Volume

26

Issue

9

fYear

1991

fDate

9/1/1991 12:00:00 AM

Firstpage

1317

Lastpage

1321

Abstract

A chip implementing the coordinate rotation digital computer (CORDIC) algorithm is described. It contains a 10-MHz 16-b fixed-point CORDIC arithmetic unit, 2-kb RAM, a controller, and input/output (I/O) registers. A modified data-path architecture allows cross-wire free data flow. The chip design involved development of optimized carry-select adders and a modified programmable-logic-array (PLA) cell layout, which allows speed increase in single-layer metal technology. The authors designed, fabricated, and tested a general-purpose fully parallel programmable CORDIC chip in CMOS technology and developed optimal iteration sequences

Keywords

CMOS integrated circuits; computerised signal processing; digital signal processing chips; parallel algorithms; parallel architectures; 10 MHz; 16 bit; 2 kbit; CMOS technology; DSP; PLA cell layout; carry-select adders; coordinate rotation digital computer; cross-wire free data flow; data-path architecture; digital signal processing applications; fixed-point CORDIC arithmetic unit; fully parallel chip; optimal iteration sequences; programmable CORDIC chip; programmable-logic-array; single-layer metal technology; Adders; CMOS technology; Chip scale packaging; Computer architecture; Design optimization; Digital signal processing chips; Fixed-point arithmetic; Read-write memory; Registers; Signal processing algorithms;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.84950

Filename

84950