Title :
Modelling delay and crosstalk in VLSI interconnect for electrical simulation
Author :
Maffezzoni, P. ; Branbilla, A.
Author_Institution :
Dipt. di Elettronica e Inf., Politecnico di Milano, Italy
fDate :
5/11/2000 12:00:00 AM
Abstract :
A method for extracting the multi-pen equivalent network of a system of m distributed RC lines is presented. The technique enables the time delays and crosstalk between interconnects to be efficiently analysed by employing conventional circuit simulators
Keywords :
delays; VLSI interconnect; circuit simulators; crosstalk; delay; distributed RC lines; electrical simulation; multi-pen equivalent network;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:20000676
