Fault-Tolerant System Using 3-Value Logic Circuits

A ternary decision circuit implemented in CMOS technology is proposed. It can be used in a duplex binary fault-tolerant system to replace both the matcher and the switch circuit. The resultant system is simpler than the conventional one. The reliable design of the ternary decision circuit is discussed in detail. A duplex 2-of-3-value fault-tolerant system can be formed by two 2-of-3-value processors and a TDC. This system is more powerful than a duplex binary system since it can provide automatic error correcting function for certain faults. All single faults can be divided into self-checked faults and secure faults. For any self-checked faults, the TDC is self-testing, strongly fault secure, and totally self-checking. For any secure faults, the TDC is strongly fault secure.