Erase/write cycle tests of n-MOSFETs with Si-implanted gate-SiO2

To discuss the applicability of a MOSFET with Si-implanted gate-SiO₂ of 50 nm thickness to a non volatile random access memory (NVRAM) operating more than 3.3×10¹⁵ erase/write (E/W) cycles, E/W-cycle tests were performed up to 10¹¹ cycles by measuring the hysteresis curve observed in a source follower MOSFET in which a sine-wave voltage of 100 kHz was supplied to the gate. Degradations in the threshold-voltage window of 15 V and gain factor were scarcely observed in a MOSFET with Si-implantation at 50 keV/1×10¹⁶ cm^-2 at a gate voltage of ±40 V. Those degradations observed in a MOSFET with 25 keV/3×10¹⁶ cm^-2 were improved by lowering the gate voltage from ±40 V to ±30 V in sacrificing the smaller threshold-voltage window from 20 to 8.5 V