Simplified and accurate power-analysis method for deep-submicron ASIC designs

The algorithm, called Simplified Power Equations (SPE), derived on the basis of a host of transistor level power analyses of standard cells, properly represents the dependency of average power dissipation on output load, input slope and input state. Using the algorithm, power models of standard cells are significantly simplified while preserving a high level of accuracy. The efficiency of a gate-level power analysis is improved due to the simplicity of the power models. The algorithm can be extended to register transfer level (RTL) power analysis with the introduction of an RTL library