Area-Efficient Temporally Hardened by Design Flip-Flop Circuits

Two temporally hardened master-slave flip-flops are presented. Both designs utilize master latches containing Muller C-elements and dual redundant temporal hardening, as well as spatially interleaved circuits in both the master and slave latches to obtain large critical node spacing for immunity to multiple node charge collection. Heavy ion test results on the first flip-flop, which uses a DICE slave latch, demonstrates effectiveness of the temporal hardening approach. The second design uses a temporally hardened slave latch, which also hardens the flip-flop against clock transients. The use of automated CAD synthesis and layout techniques using these multibit flip-flops is also described, as is the hardening impact on design size and power.