Low cost VLSI architecture of resisting long echo channel estimation for DTMB system

Digital television/terrestrial multimedia broadcasting (DTMB) was announced as the Chinese digital television terrestrial broadcasting (DTTB) standard in August, 2006. It adopts TDS-OFDM (time-domain synchronous-orthogonal frequency division multiplexing) as the baseline modulation technology. There is not pilot information in order to avoid reduction of channel throughput. It uses pseudo-noise (PN) sequence as guard interval (GI) and the training sequence for both multi- and single-carrier block transmissions which makes the synchronization faster than CP-OFDM (cyclic prefix-orthogonal frequency division multiplexing) systems. It can resist the inter-symbol interference (ISI) and can be used for channel estimation and synchronization. In this paper, a full-mode channel estimation scheme for DTMB demodulator is developed. This method utilizes the PN sequence to obtain channel estimation and equalization both in three kinds of frame head (FH) mode as well as in single and multi-carrier modulation transmission mode. To implement on hardware realization, interference cancellation is predigested, then equalization and filter for channel impulse response are optimized. A low cost VLSI architecture for channel estimation and equalization is proposed which works effectually and achieves low complexity as well. Computational simulation results show that the proposed scheme has little BER loss in performance.