A 3-D Cache With Ultra-Wide Data Bus for 3-D Processor-Memory Integration

Author

Zia, Aamir ; Jacob, Philip ; Kim, Jin-Woo ; Chu, Michael ; Kraft, Russell P. ; McDonald, John F.

Author_Institution

Electr., Comput. & Syst. Eng. Dept., Rensselaer Polytech. Inst., Troy, NY, USA

Volume

18

Issue

6

fYear

2010

fDate

6/1/2010 12:00:00 AM

Firstpage

967

Lastpage

977

Abstract

Slow cache memory systems and low memory bandwidth present a major bottleneck in performance of modern microprocessors. 3-D integration of processor and memory subsystems provides a means to realize a wide data bus that could provide a high bandwidth and low latency on-chip cache. This paper presents a three-tier, 3-D 192-kB cache for a 3-D processor-memory stack. The chip is designed and fabricated in a 0.18 m fully depleted SOI CMOS process. An ultra wide data bus for connecting the 3-D cache with the microprocessor is implemented using dense vertical vias between the stacked wafers. The fabricated cache operates at 500 MHz and achieves up to 96 GB/s aggregate bandwidth at the output.

Keywords

CMOS integrated circuits; cache storage; microprocessor chips; silicon-on-insulator; 3D cache; 3D processor-memory integration; CMOS process; frequency 500 MHz; memory size 192 KByte; silicon-on-insulator; size 0.18 mum; ultrawide data bus; 3-D integration; FD-SOI; SRAM; cache architecture; data bus;

fLanguage

English

Journal_Title

Very Large Scale Integration (VLSI) Systems, IEEE Transactions on

Publisher

ieee

ISSN

1063-8210

Type

jour

DOI

10.1109/TVLSI.2009.2017750

Filename

5223675