Variability Induced by Line Edge Roughness in Double-Gate Dopant-Segregated Schottky MOSFETs

Intrinsic parameter fluctuations introduced by process variations, such as line edge roughness (LER), create an increasing challenge to the CMOS technology scaling. In this paper, variations in double-gate dopant-segregate Schottky (DSS) MOSFETs, caused by LER of silicon-fin, are systematically investigated using statistical technology computer-aided design simulations. The impact of LER on both Schottky barrier and DSS-MOSFETs are examined contrastively. The results show that DSS-MOSFETs offer a larger and more uniform drive current, but suffer a more serious Vt fluctuation. The cause of such larger Vt flutuation is also analyzed, thus providing a good starting point to propose way to solve this problem.