Title :
A fast-acquisition PLL using split half-duty sampled feedforward loop filter
Author :
Shin, Woo-Yeol ; Kim, Manho ; Hong, Gi-Moon ; Kim, Suhwan
Author_Institution :
Electr. Eng. & Comput. Sci., Seoul Nat. Univ., Seoul, South Korea
Abstract :
We reduce the pattern jitter and acquisition time of a phase-locked loop (PLL) by adopting the split half-duty sampled feedforward loop filter. A prototype designed and fabricated in a 0.18μm standard CMOS technology has a 40% lower acquisition time than a PLL without operating in fast acquisition mode. Its peak-to-peak jitter is 26% less than that of a PLL with a conventional 2nd-order RC loop filter.
Keywords :
CMOS analogue integrated circuits; filters; jitter; phase locked loops; CMOS technology; acquisition time; fast-acquisition PLL; pattern jitter; peak-to-peak jitter; phase-locked loop; size 0.18 mum; split half-duty sampled feedforward loop filter; Capacitance; Capacitors; Charge pumps; Electrical engineering; Feedforward neural networks; Jitter; Phase locked loops; Acquisition time, loop filter, pattern jitter, phase locked loop (PLL);
Journal_Title :
Consumer Electronics, IEEE Transactions on
DOI :
10.1109/TCE.2010.5606337
