Self-generating clock using an augmented distribution network

VLSI sub-modules can be designed in a synchronous style but with a local clock generated using its own distribution network as a ring oscillator. If a long critical path exists, a delay can be added to the oscillator path by implementing the critical path (alone) in self-timed logic. This technique has many of the advantages of self-timed logic with lower circuit overheads and a conventional design style. The technique is illustrated by a self-timed square-root module