Simulator for path-delay faults on mixed-level circuits

Most of the available path-delay fault simulators for scan environments rely on the use of augmented scan flip-flops and exclusively consider circuits composed of only discrete gates. This paper describes an efficient path-delay fault simulator which operates in standard scan environments. The new simulator based on a parallel pattern fault simulation algorithm can handle the switching devices by using new logic values. To achieve high-speed performance, two different sets of logic values are used for the element evaluation according to the device level. The results show the efficiency of the simulator