Band-to-Band Tunneling Ballistic Nanowire FET: Circuit-Compatible Device Modeling and Design of Ultra-Low-Power Digital Circuits and Memories

Band-to-band tunneling (BTBT) nanowire FETs have been studied as a possible successor to CMOS FETs. In the literature, it has already been shown that a 1-D p⁺-i- n⁺-type semiconductor nanowire governed by a BTBT transport mechanism offers a subthreshold swing lower than the conventional limit of 60 mV/dec while maintaining a reasonable on-state performance. The concept of BTBT nanowire FETs is primitive, and the manufacturing process is nascent. In the absence of a suitable device model and/or a reliable circuit simulator, the evaluation and impact of such novel transistors are difficult to estimate. In this paper, we propose a simple complementary device model for BTBT nanowire FETs suitable for multitransistor circuit simulation and evaluate its performance in the ballistic limit. The device models so developed have been used to simulate a class digital logic circuits and dynamic memories (e.g., DRAM) to analyze their suitability in future very large scale integration design. Circuit level simulations explicitly show that the proposed p⁺ -i-n⁺-type BTBT nanowire FETs are well suited for medium throughput (approximately hundreds of kilohertz to a few tens of megahertz) ultra-low-power applications. The standby leakage power in memory and logic circuits has been found to be as low as 10^-20 W due to the inherent super cutoff nature of the device. The presence of interconnect parasitics in parallel with intrinsic device capacitance severely limits the performance of digital circuits. The impact of interconnect parasitics on the performance of BTBT nanowire FETs has also been studied.