DocumentCode
1358842
Title
Identifying defects in deep-submicron CMOS ICs
Author
Soden, J.M. ; Hawkins, C.F. ; Miller, A.C.
Author_Institution
Sandia Nat. Labs., Albuquerque, NM, USA
Volume
33
Issue
9
fYear
1996
Firstpage
66
Lastpage
71
Abstract
With safety margins for reliability, test, failure analysis, and design verification shrinking, it would be a shame to give up the I/sub DDQ/ technique-and luckily, we may not have to. Steps can be taken to maintain its applicability as we rush deeper into the submicron regime. We will first examine why the I/sub DDQ/ test serves several interests, then describe the challenge posed by 0.35-0.07 μm transistor geometries, and finally propose several solutions.
Keywords
CMOS integrated circuits; electric current measurement; failure analysis; integrated circuit reliability; integrated circuit testing; 0.35 to 0.07 micron; I-V signatures; I/sub DDQ/ technique; SIA Roadmap ICs; deep-submicron CMOS IC; defects identification; failure analysis; reliability; CMOS integrated circuits; Circuit testing; Current measurement; Current supplies; Electromigration; Failure analysis; Life testing; Microelectronics; Power supplies; Reliability engineering;
fLanguage
English
Journal_Title
Spectrum, IEEE
Publisher
ieee
ISSN
0018-9235
Type
jour
DOI
10.1109/6.535396
Filename
535396
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