Polysilicon Nanowire Transistors and Arrays Fabricated With the Multispacer Technique

In this paper, we demonstrate the ability of the multi spacer patterning technique to yield layers of polycrystalline silicon nanowires with a sublithographic pitch, by exclusively using micrometer resolution and CMOS processing steps. We characterize single spacers operating as poly-Si nanowire field effect transistors. We demonstrate also the possibility to lay a spacer perpendicularly to a set of parallel spacers in a crossbar fashion. The extrapolated cross-point density from the small 4 × 1-array is in the range of 10¹⁰cm^-2. We discuss the applications of this technique to improve the density of previously reported poly-SiNW memories and as a future framework for nanowire crossbars and decoders. Then we analyze the limitations and costs of the proposed technique.