Title :
Design for velocity saturated, short-channel CMOS drivers with simultaneous switching noise and switching time considerations
Author :
Yang, Yaochao ; Brews, John R.
Author_Institution :
Div. of Interactive Syst., Silicon Graphics Comput. Syst., Mountain View, CA, USA
fDate :
9/1/1996 12:00:00 AM
Abstract :
Design guidelines for velocity-saturated, short-channel CMOS drivers are presented in this paper based on approximating the package inductance by an effective, lumped, power-supply bus parasitic inductance. A worst-case maximum simultaneous switching noise VGM and gate propagation delay time tD,1/2 are treated as performance constraints for which driver design tradeoffs between driver geometry, the maximum number of simultaneously switched drivers, and the effective inductance are obtained. For typical loading conditions, design examples based on the proposed guidelines are shown by SPICE simulations using the MOS3 model to agree with both design goals within 10%
Keywords :
CMOS logic circuits; delays; driver circuits; inductance; integrated circuit design; integrated circuit noise; integrated circuit packaging; switching; MOS3 model; SPICE simulations; design guidelines; driver geometry; effective lumped inductance; gate propagation delay time; package inductance; performance constraints; power-supply bus parasitic inductance; short-channel CMOS drivers; simultaneous switching noise; switching time; velocity saturated drivers; Delay effects; Driver circuits; Electronics packaging; Guidelines; Inductance; Propagation delay; SPICE; Semiconductor device noise; Switches; Voltage;
Journal_Title :
Solid-State Circuits, IEEE Journal of
