An ultra-low-power-consumption high-speed GaAs quasi-differential switch flip-flop (QD-FF)

Author

Maeda, Tadashi ; Numata, Keiichi ; Fujii, Masahiro ; Tokushima, Masatoshi ; Wada, Shigeki ; Fukaishi, Muneo ; Ishikawa, Masaoki

Author_Institution

Microelectron. Res. Labs., NEC Corp., Ibaraki, Japan

Volume

31

Issue

9

fYear

1996

fDate

9/1/1996 12:00:00 AM

Firstpage

1361

Lastpage

1363

Abstract

The developed GaAs static flip-flop operates at a data rate of 10 Gb/s with a power consumption of 2.8 mW at a supply voltage of 0.6 V. The power consumption at 10 Gb/s is 1/3 that of the lowest reported value for D-FFs. A divider using the QD-FF configuration operates at a clock frequency of 16 GHz with a power consumption of 2.4 mW at a supply voltage of 0.6 V. The power-delay product is about one-third that of the lowest reported value for dividers

Keywords

III-V semiconductors; JFET integrated circuits; dividing circuits; field effect logic circuits; flip-flops; gallium arsenide; integrated circuit design; large scale integration; logic design; 0.6 V; 10 Gbit/s; 16 GHz; 2.4 mW; 2.8 mW; GaAs; GaAs static flip-flop; HJFET technology; divider implementation; high-speed flip-flop; quasi-differential switch type; ultra-low-power-consumption; Circuits; Clocks; Delay; Energy consumption; FETs; Flip-flops; Gallium arsenide; Latches; Switches; Voltage;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.535426

Filename

535426