Differential CMOS edge-triggered flip-flop based on clock racing

A differential CMOS edge-triggered flip-flop is proposed that employs a pair of cross-coupled inverters, providing fully static operation. The edge-triggering operation is achieved by a narrow pulse, produced by the clock signal and its inverted delayed version. The proposed flip-flop exhibits significant power savings of up to 25% when compared with other static differential flip-flop circuits, maintaining its speed advantage for different power supply voltages and data activity rates. It also requires only 12 transistors resulting in a reduced transistor count. Moreover, unlike the existing differential circuits, it has the ability to operate under a reduced swing clock signal without static power dissipation