A 12.3-mW 12.5-Gb/s Complete Transceiver in 65-nm CMOS Process

A 12.3-mW 12.5-Gb/s complete transceiver based on the 65-nm standard digital CMOS process was developed. The chip includes a clock-and-data-recovery (CDR) device, a multiplexer/demultiplexer (MUX/DEMUX), and a global clock-distribution network. To reduce power consumption, a low-swing voltage-mode driver with pulse-current boosting and an LC resonant-clock distribution with distributed on-chip inductors are used in the transmitter, while a symbol-rate phase detector (SPD) using a three-stage sense amplifier and phase-rotating phase-locked loop (PLL) with variable delay are used in the receiver. The transceiver operates at a bit error rate (BER) of 10^-12 or less through a 20-cm test board with total attenuation of -12.1 dB while consuming power of 0.98 mW/(Gb/s) per transceiver.