DocumentCode :
1359234
Title :
A 10 MS/s 11-bit 0.19 mm 
Algorithmic ADC With Improved Clocking Scheme
Author :
Kim, Min Gyu ; Hanumolu, Pavan Kumar ; Moon, Un-Ku
Author_Institution :
Sch. of Electr. Eng. & Comput. Sci., Oregon State Univ., Corvallis, OR, USA
Volume :
44
Issue :
9
fYear :
2009
Firstpage :
2348
Lastpage :
2355
Abstract :
A 10 MS/s 11-bit algorithmic ADC with an active area of 0.19 mm2 is presented. Using an improved clocking scheme, this design overcomes the speed limit of algorithmic ADCs. The proposed ADC employs amplifier sharing, DC offset cancellation, and input memory effect suppression, resulting in reduced area and power, and high linearity. The ADC implemented in a 0.13 mum thick gate-oxide CMOS process achieves 69 dB SFDR, 58 dB SNR, and 56 dB SNDR, while consuming 3.5 mA from a 3 V supply.
Keywords :
CMOS integrated circuits; analogue-digital conversion; clocks; DC offset cancellation; algorithmic ADC; amplifier sharing; current 3.5 mA; improved clocking scheme; input memory effect suppression; size 0.13 mum; thick gate-oxide CMOS process; voltage 3 V; Algorithm design and analysis; Bandwidth; CMOS technology; Capacitors; Clocks; Differential amplifiers; Frequency; Hardware; Multiplexing; Voltage; Algorithmic ADC; amp sharing; clocking scheme; delay-locked loop; memory effect; system-on-chip;
fLanguage :
English
Journal_Title :
Solid-State Circuits, IEEE Journal of
Publisher :
ieee
ISSN :
0018-9200
Type :
jour
DOI :
10.1109/JSSC.2009.2023158
Filename :
5226753
Link To Document :
