Energy–Performance Tunable Logic

We propose a new logic family that enables the user to tune the transistor´s effective threshold voltage after fabrication for higher speed or lower power. This technique along with dynamic voltage scaling allows simultaneous optimization of static and dynamic power based on the application/workload requirements. Programmable interconnect from an FPGA was implemented using this logic family on a 90 nm CMOS test chip. Measurements show that this topology provides twice the tuning range in the energy-performance space compared to a conventional interconnect utilizing only supply voltage scaling. For most of the performance range, this circuit consumes 35% less energy compared to a state-of-the-art design. The circuit is an externally static, internally pulse-mode topology which can replace static circuits without requiring significant changes to the system.