Title :
A 12-Bit 200-MHz CMOS ADC
Author :
Sahoo, Bibhu Datta ; Razavi, Behzad
Author_Institution :
Electr. Eng. Dept., Univ. of California, Los Angeles, CA, USA
Abstract :
A pipelined ADC incorporates a blind LMS calibration algorithm to correct for capacitor mismatches, residue gain error, and op amp nonlinearity. The calibration applies 128 levels and their perturbed values, computing 128 local errors across the input range and driving the mean square of these errors to zero. Fabricated in 90-nm digital CMOS technology, the ADC achieves a DNL of 0.78 LSB, an INL of 1.7 LSB, and an SNDR of 62 dB at an analog input frequency of 91 MHz while consuming 348 mW from a 1.2 V supply.
Keywords :
CMOS integrated circuits; analogue-digital conversion; least mean squares methods; CMOS analog-digital convertors; adaptive systems; blind least mean square; capacitor mismatch; frequency 200 MHz; frequency 91 MHz; power 348 mW; size 90 nm; voltage 1.2 V; word length 12 bit; Analog-digital conversion; CMOS technology; Calibration; Capacitors; Error correction; Frequency; Helium; Least squares approximation; Operational amplifiers; Voltage; Adaptive systems; blind least mean square (LMS) calibration; low-gain op amp; nonlinearity correction; pipelined analog-to-digital converter;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.2009.2024809
