DocumentCode
1359450
Title
Dual-loop DLL-based clock synchroniser
Author
Hwang, Sung-Sik
Volume
36
Issue
14
fYear
2000
fDate
7/6/2000 12:00:00 AM
Firstpage
1173
Lastpage
1174
Abstract
A clock synchronisation scheme based on a newly proposed dual-loop delay locked loop (DLL) is presented. The proposed scheme incorporates analogue and digital DLLs to align phases of two different frequency clocks. Simulation results show that the internal clock can be synchronised to the reference clock by tracking the dual feedback loop. The whole circuit design was implemented using 0.35 μm CMOS technology. Power dissipation is ~42 mW with a single 3.3 V supply
Keywords
CMOS integrated circuits; circuit feedback; delay lock loops; mixed analogue-digital integrated circuits; synchronisation; timing circuits; 0.35 micron; 3.3 V; 42 mW; CMOS technology; DLL-based clock synchroniser; analogue DLLs; clock synchronisation scheme; delay locked loop; digital DLLs; dual feedback loop tracking; dual-loop DLL; internal clock; reference clock;
fLanguage
English
Journal_Title
Electronics Letters
Publisher
iet
ISSN
0013-5194
Type
jour
DOI
10.1049/el:20000844
Filename
852222
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