Title :
Bit line sensing strategy for testing for data retention faults in CMOS SRAMs
Author :
Champac, V.H. ; Avendano, V. ; Linares, M.
Author_Institution :
Dept. of Electron. Eng., INAOE, Puebla, Mexico
fDate :
7/6/2000 12:00:00 AM
Abstract :
A strategy for testing for data retention faults in CMOS static random access memories (SRAMs) is proposed. Sensing the voltage at one of the data bus lines with a proper design for testability (DFT) reading circuitry enables the fault-free memory cells from any defective cell(s) to be determined. DFT reading circuitry is also proposed. An analysis of the cost of the proposed approach in terms of area, test time and performance degradation is presented
Keywords :
CMOS memory circuits; SRAM chips; design for testability; fault location; integrated circuit testing; CMOS SRAM; DFT reading circuitry; bit line sensing strategy; data bus lines; data retention faults; design for testability; static RAM testing; static random access memories;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:20000855
