High-Performance Silicon Nanowire Gate-All-Around nMOSFETs Fabricated on Bulk Substrate Using CMOS-Compatible Process

Author

Song, Yi ; Zhou, Huajie ; Xu, Qiuxia ; Niu, Jiebin ; Yan, Jiang ; Zhao, Chao ; Zhong, Huicai

Author_Institution

Inst. of Microelectron., Chinese Acad. of Sci., Beijing, China

Volume

31

Issue

12

fYear

2010

Firstpage

1377

Lastpage

1379

Abstract

In this letter, a novel self-aligned CMOS-compatible method for the fabrication of gate-all-around silicon nanowire MOSFETs (GAA SNWFETs) on bulk substrate has been proposed. The fabricated SNWFET featuring 33-nm gate length and 7-nm diameter shows the highest driving current (I_on = 2500 μA/μm at V_ds = V_gs = 1.0 V) among previously reported data and achieves high I_on/I_off ratio of 10⁵, lightening the promise for high performance and strong scalability of GAA SNWFETs. The process details and optimization procedure are extensively discussed.

Keywords

CMOS integrated circuits; MOSFET; elemental semiconductors; nanowires; silicon; CMOS-compatible process; Si; bulk substrate; high-performance silicon nanowire gate-all-around nMOSFET; stress-limited oxidation; CMOS integrated circuits; Logic gates; MOSFETs; Nanostructured materials; Oxidation; Substrates; Bulk gate-all-around silicon nanowire MOSFETs (GAA SNWFETs); parasitic effects; stress-limited oxidation; volume inversion;

fLanguage

English

Journal_Title

Electron Device Letters, IEEE

Publisher

ieee

ISSN

0741-3106

Type

jour

DOI

10.1109/LED.2010.2080256

Filename

5608490