Title :
Low Cost Hardware Implementation of Logarithm Approximation
Author :
Gutierrez, R. ; Valls, J.
Author_Institution :
Dept. de Fis. y Arquitectura de Comput., Univ. Miguel Hernandez, Alicante, Spain
Abstract :
A low cost, high-speed architecture for the computation of the binary logarithm is proposed. It is based on the Mitchell approximation with two correction stages: a piecewise linear interpolation with power-of-two slopes and truncated mantissa, and a LUT-based correction stage that correct the piecewise interpolation error. The architecture has been implemented in an FPGA device and the results are compared with other low cost architectures requiring less area and achieving high-speed.
Keywords :
approximation theory; computer architecture; digital arithmetic; field programmable gate arrays; interpolation; table lookup; FPGA device; Mitchell approximation; binary logarithm; correction stages; hardware implementation; logarithm approximation; lookup table; piecewise interpolation error; piecewise linear interpolation; power-of-two slopes; truncated mantissa; Accuracy; Error correction; Linear approximation; Piecewise linear approximation; Logarithm approximation; Mitchell´s error correction; piecewise linear approximation;
Journal_Title :
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
DOI :
10.1109/TVLSI.2010.2081387
