DocumentCode
1360465
Title
A BIST and boundary-scan economics framework
Author
Miranda, José M.
Author_Institution
Lucent Technol., Bell Labs., Princeton, NJ, USA
Volume
14
Issue
3
fYear
1997
Firstpage
17
Lastpage
23
Abstract
IC level built-in self-test and IEEE 1149.1 boundary-scan architecture offer potential benefits at all phases of a product´s life cycle: development, manufacturing, and field deployment. During early model debugging, for example, boundary scan rapidly flushes out structural defects such as solder bridges or opens. During manufacturing test, BIST and boundary scan can improve coverage, reduce test and diagnosis time, and reduce test capital. In the field, embedded boundary-scan and BIST capabilities may facilitate accurate system diagnostics that isolate defects to individual field-replaceable units. Before investing in these design-for-testability features, however, a product development team should carefully consider their costs as well as their benefits. So far, tools for accurately evaluating these economic trade offs have not been available. At Lucent Technologies, therefore, we have developed a framework to guide a cost-benefit analysis of an investment in BIST and/or boundary scan. The framework is in its formative stages and will continue to evolve. BIST and boundary scan affect cost at all levels of product integration and during all phases of the product life cycle. This analysis framework helps developers decide if the benefits are worth the costs
Keywords
boundary scan testing; built-in self test; cost-benefit analysis; integrated circuit testing; BIST; IEEE 1149.1 boundary-scan architecture; Lucent Technologies; boundary-scan economics framework; built-in self-test; cost-benefit analysis; early model debugging; field deployment; field-replaceable units; manufacturing; product development team; product life cycle; solder bridges; structural defects; system diagnostics; Application specific integrated circuits; Built-in self-test; Computer architecture; Costs; Design for testability; Hardware; Manufacturing; Personnel; Software architecture; System testing;
fLanguage
English
Journal_Title
Design & Test of Computers, IEEE
Publisher
ieee
ISSN
0740-7475
Type
jour
DOI
10.1109/54.605988
Filename
605988
Link To Document