DocumentCode :
1360598
Title :
The test of time. Clock-cycle estimation and test challenges for future microprocessors
Author :
Fisher, Phil D. ; Nesbitt, Robert
Author_Institution :
Sematech, Austin, TX, USA
Volume :
14
Issue :
2
fYear :
1998
fDate :
3/1/1998 12:00:00 AM
Firstpage :
37
Lastpage :
44
Abstract :
Even with aggressive new technology, the complex high-performance processor will require special design techniques and architectures to take advantage of new interconnect and transistor technology. Microprocessor on-chip clock frequencies of multiple GHz are predicted for future generations. However, significant development is necessary in technology, manufacturing, and design CAD tools in order to achieve the performance, manufacturability, and reliability desired for these future products. Design must own the test function. The ability of test to continue supporting at-speed testing has reached physical limits as well as cost impacts that will make testing a very high design priority
Keywords :
clocks; integrated circuit design; integrated circuit interconnections; integrated circuit reliability; integrated circuit testing; microprocessor chips; CAD tools; at-speed testing; clock-cycle estimation; cost impacts; design priority; design techniques; interconnect; manufacturability; microprocessors; on-chip clock frequencies; physical limits; reliability; test challenges; Circuit testing; Clocks; Computer aided instruction; Cost function; Delay; Electronics industry; Frequency; Integrated circuit interconnections; Microprocessors; Semiconductor device testing;
fLanguage :
English
Journal_Title :
Circuits and Devices Magazine, IEEE
Publisher :
ieee
ISSN :
8755-3996
Type :
jour
DOI :
10.1109/101.666590
Filename :
666590
Link To Document :
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