Variable-Latency Floating-Point Multipliers for Low-Power Applications

This paper proposes a variable-latency floating-point multiplier architecture, which is compliant with IEEE 754-1985 and suitable for low-power applications. The architecture splits the significand multiplier into the upper and lower parts, and predicts the carry bit, sticky bit, and significand product from the upper part. In the case of correct prediction, the computation of lower part is disabled and the rounding operation is significantly simplified so that the floating-point multiplication can consume less power, and be completed early while maintaining the correct IEEE rounding and product. Experimental results show that the proposed multiplier can save respectable power and energy when compared to the fast multiplier at the expense of slight area and acceptable delay overheads.